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| BUK9006-55A TrenchMOSTM logic level FET Rev. 01 -- 1 August 2003 Preliminary data 1. Product profile 1.1 Description N-channel enhancement mode field-effect power transistor available as a bare die using Philips General Purpose Automotive (GPA) TrenchMOSTM technology. Product availability: BUK9006-55A distributed as individual die on reel. 1.2 Features s 25 A testing of individual die s Inductive energy testing of individual die s Life-tested to Q101 at 175 C s Automatic visual inspection. 1.3 Applications s Automotive systems s Motors, lamps and solenoids s 12 V and 24 V loads s General purpose power switching. 1.4 Quick reference data s EDS(AL)S 1.1 J s V(BR)DSS 55 V s Die size = 4.30 x 4.30 mm (typ) s RDSon(die) = 5 m (typ) s VGS(th) = 1.5 V (typ) s Die thickness = 240 m (typ). 2. Pinning information Table 1: Pin 1 2 Pinning - Bare die simplified outline and symbol Description gate d Simplified outline Symbol source drain; connected to underside of die 1 2 g s MBB076 03nn81 Philips Semiconductors BUK9006-55A TrenchMOSTM logic level FET 3. Limiting values Table 2: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDS VDGR VGS ID IDM Tstg Tj IDR IDRM EDS(AL)S Parameter drain-source voltage (DC) drain-gate voltage (DC) gate-source voltage (DC) drain current (DC) peak drain current storage temperature junction temperature reverse drain current (DC) peak reverse drain current non-repetitive drain-source avalanche energy Tmb = 25 C Tmb = 25 C; pulsed; tp 10 s unclamped inductive load; ID = 25 A; VDS 55 V; VGS = 5 V; RGS = 50 ; starting Tj = 25 C [1] Conditions RGS = 20 k Tmb = 25 C; VGS = 5 V Tmb = 100 C; VGS = 5 V Tmb = 25 C; pulsed; tp 10 s [1] [1] Min -55 -55 - Max 55 55 15 125 88 503 +175 +175 125 503 1.1 Unit V V V A A A C C A A J Source-drain diode Avalanche ruggedness [1] Calculated with Rth(j-mb) = 0.59 K/W. 9397 750 11571 (c) Koninklijke Philips Electronics N.V. 2003. All rights reserved. Preliminary data Rev. 01 -- 1 August 2003 2 of 10 Philips Semiconductors BUK9006-55A TrenchMOSTM logic level FET 4. Characteristics Table 3: Characteristics Tj = 25 C unless otherwise specified. Symbol V(BR)DSS Parameter drain-source breakdown voltage Conditions ID = 0.25 mA; VGS = 0 V Tj = 25 C Tj = -55 C VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Figure 5 Tj = 25 C Tj = 175 C Tj = -55 C IDSS drain-source leakage current VDS = 55 V; VGS = 0 V Tj = 25 C Tj = 175 C IGSS RDSon(die) gate-source leakage current die drain-source on-state resistance VGS = 15 V; VDS = 0 V VGS = 5 V; ID = 25 A; Figure 4 Tj = 25 C Tj = 175 C Dynamic characteristics Qg(tot) Qgs Qgd Ciss Coss Crss td(on) tr td(off) tf VSD trr Qr total gate charge gate-source charge gate-drain (Miller) charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time source-drain (diode forward) voltage reverse recovery time recovered charge IS = 25 A; VGS = 0 V; Figure 11 IS = 20 A; dIS/dt = -100 A/s VGS = -10 V; VDS = 30 V VDS = 30 V; RL = 1.2 ; VGS = 5 V; RG = 10 VGS = 0 V; VDS = 25 V; f = 1 MHz; Figure 8 VGS = 5 V; VDS = 44 V; ID = 25 A; Figure 10 92 11 43 4550 760 500 40 175 280 167 0.85 70 160 6020 900 690 1.2 nC nC nC pF pF pF nS nS nS nS V ns nC 5 6 12 m m 0.05 2 10 500 100 A A nA 1 0.5 1.5 2 2.3 V V V 55 50 V V Min Typ Max Unit Static characteristics Source-drain diode 9397 750 11571 (c) Koninklijke Philips Electronics N.V. 2003. All rights reserved. Preliminary data Rev. 01 -- 1 August 2003 3 of 10 Philips Semiconductors BUK9006-55A TrenchMOSTM logic level FET 400 ID (A) 300 10 8 6 03nn87 9 RDSon (m) 8 03nn86 Label is VGS (V) 5 4.8 4.6 4.4 4.2 4 200 100 0 0 2 4 3.8 3.6 3.4 3.2 3 2.8 2.6 2.4 2.2 6 8 10 VDS (V) 7 6 5 0 5 10 VGS (V) 15 Tj = 25 C; tp = 300 s Tj = 25 C; ID = 25 A Fig 1. Output characteristics: drain current as a function of drain-source voltage; typical values. Fig 2. Drain-source on-state resistance as a function of gate-source voltage; typical values. 20 RDSon (m) 3 3.2 3.4 3.6 3.8 4 03nn88 2 a 1.5 03ne89 Label is VGS (V) 15 1 10 5 0.5 10 5 0 100 200 300 ID (A) 400 0 -60 0 60 120 Tj (C) 180 Tj = 25 C; tp = 300 s R DSon a = ---------------------------R DSon ( 25 C ) Fig 4. Normalized drain-source on-state resistance factor as a function of junction temperature. Fig 3. Drain-source on-state resistance as a function of drain current; typical values. Remark: Figures 1, 2, and 3 measured on die assembled in SOT78 with 3 x 350 m source bond wires. 9397 750 11571 (c) Koninklijke Philips Electronics N.V. 2003. All rights reserved. Preliminary data Rev. 01 -- 1 August 2003 4 of 10 Philips Semiconductors BUK9006-55A TrenchMOSTM logic level FET 2.5 VGS(th) (V) 2 max 03aa33 10-1 ID (A) 10-2 03aa36 1.5 typ 10-3 min typ max 1 min 10-4 0.5 10-5 0 -60 0 60 120 Tj (C) 180 10-6 0 1 2 VGS (V) 3 ID = 1 mA; VDS = VGS Tj = 25 C; VDS = VGS Fig 5. Gate-source threshold voltage as a function of junction temperature. Fig 6. Sub-threshold drain current as a function of gate-source voltage. 120 gfs (S) 03nn84 12000 C (pF) Coss 8000 Crss Ciss 03nn89 80 40 4000 0 0 20 40 60 ID (A) 80 0 10-2 10-1 1 10 VDS (V) 102 Tj = 25 C; VDS = 25 V VGS = 0 V; f = 1 MHz Fig 7. Forward transconductance as a function of drain current; typical values. Fig 8. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values. 9397 750 11571 (c) Koninklijke Philips Electronics N.V. 2003. All rights reserved. Preliminary data Rev. 01 -- 1 August 2003 5 of 10 Philips Semiconductors BUK9006-55A TrenchMOSTM logic level FET 100 ID (A) 75 03nn85 5 VGS (V) 4 VDD = 14 V 3 03nn83 50 2 VDD = 44 V 25 Tj = 175 C Tj = 25 C 1 0 0 1 2 3 VGS (V) 4 0 0 25 50 75 QG (nC) 100 VDS = 25 V Tj = 25 C; ID = 25 A Fig 9. Transfer characteristics: drain current as a function of gate-source voltage; typical values. Fig 10. Gate-source voltage as a function of gate charge; typical values. 100 IS (A) 75 03nn82 50 25 Tj = 175 C Tj = 25 C 0 0.0 0.3 0.6 0.9 VSD (V) 1.2 VGS = 0 V Fig 11. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values. Remark: Figures 9, 10, and 11 measured on die assembled in SOT78 with 3 x 350 m source bond wires. 9397 750 11571 (c) Koninklijke Philips Electronics N.V. 2003. All rights reserved. Preliminary data Rev. 01 -- 1 August 2003 6 of 10 Philips Semiconductors BUK9006-55A TrenchMOSTM logic level FET 5. Bare die outline G H L D M P-P N Drain connection made to underside. A F 1 P 2 P B E TYPICAL DIMENSIONS UNIT mm A 4.30 B 4.30 D 3.36 E 3.62 F 0.54 G 0.4 H L M 0.27 N 0.24 0.025 03nn80 0.096 0.175 Fig 12. Bare die outline. Table 4: Parameter Top-side metallization (gate and source bond pads) Back-side metallization (drain contact) Passivation layer Bare die information Description 5 m Al + 1 % Si (sputtered) 0.1 m Ti / 0.3 m Ni / 0.1 m Ag (evaporated) 1 m Si3N4 9397 750 11571 (c) Koninklijke Philips Electronics N.V. 2003. All rights reserved. Preliminary data Rev. 01 -- 1 August 2003 7 of 10 Philips Semiconductors BUK9006-55A TrenchMOSTM logic level FET 6. Revision history Table 5: Rev Date 01 20030801 Revision history CPCN Description Preliminary data (9397 750 11571) 9397 750 11571 (c) Koninklijke Philips Electronics N.V. 2003. All rights reserved. Preliminary data Rev. 01 -- 1 August 2003 8 of 10 Philips Semiconductors BUK9006-55A TrenchMOSTM logic level FET 7. Data sheet status Level I II Data sheet status[1] Objective data Preliminary data Product status[2][3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). III Product data Production [1] [2] [3] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 8. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 10. Trademarks TrenchMOS -- is a trademark of Koninklijke Philips Electronics N.V. 9. Disclaimers Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com. 9397 750 11571 Fax: +31 40 27 24825 (c) Koninklijke Philips Electronics N.V. 2003. All rights reserved. Preliminary data Rev. 01 -- 1 August 2003 9 of 10 Philips Semiconductors BUK9006-55A TrenchMOSTM logic level FET Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . Quick reference data. . . . . . . . . . . . . . . . . . . . . Pinning information . . . . . . . . . . . . . . . . . . . . . . Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 1 1 1 1 2 3 7 8 9 9 9 9 (c) Koninklijke Philips Electronics N.V. 2003. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 1 August 2003 Document order number: 9397 750 11571 |
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